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Dr. Shreejith Shanker

Assistant Professor (Electronic & Elect. Engineering)
ARAS AN PHIARSAIGH
      
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Dr. Shreejith Shanker

Assistant Professor (Electronic & Elect. Engineering)
ARAS AN PHIARSAIGH

 SHREEJITH.SHANKER@tcd.ie

 3531896 1609


Dr. Shanker is an Assistant Professor at the Department of Electronic & Electrical Engineering at Trinity College Dublin, The University of Dublin, Ireland, since April 2019. He graduated with a Bachelors degree in Electronics & Communication Engineering from the former the University of Kerala in 2006 and a PhD degree from Nanyang Technological University and Technical University of Munich in 2016. From 2015 to 2016, he was a post-doctoral research fellow at the Hardware and Embedded Systems Lab, Nanyang Technological University, Singapore where he was working on cognitive radio architectures and techniques for commercial and aeronautical communication systems. He took up the role of Teaching Fellow at the School of Engineering, The University of Warwick, UK in 2017, where he continued his research on in-network computation and accelerators, while primarily focusing on delivering modules on Computer Architecture and Programming to the undergraduate cohort. He briefly took up the role of Research Fellow at the Electrification Suite and Test Lab , TUM CREATE Ltd, Singapore, exploring research ideas on decentralised compute systems in smart energy systems and power grids before taking up the role of Assistant Professor at Trinity College Dublin, Ireland. His current research explores reconfigurable architectures and frameworks for distributed accelerators that are tightly coupled to the network fabric, with application to autonomous systems, media processing and communication networks. He started his professional career in 2006 as a Design Engineer at Processor Systems India where he was involved in design and verification of high-speed custom logic for network switches and compute accelerators. Later, he joined the Vikram Sarabhai Space Centre, one of the premier research centres under the Indian Space Research Organisation as a Scientist working on design of real-time, mission critical subsystems for launch vehicles and satellite systems.
  Applied Electronics   ARTIFICIAL NEURAL NETWORKS   Automotive Electronics   Communication engineering, technology   Communication Systems   Communications engineering   Computer architecture   Computer Hardware   Computer Networks   Computer/Data/Network Security   Data protection, storage technology, cryptography   Digital Computers/Computing   Digital systems, representation   Distributed systems   Electrical Engineering/Electronics   Electronic circuit design   Electronic Engineering, circuit design   ELECTRONICS   Embedded computing   Field Programmable Gate Arrays (FPGAs)   High Performance Computing   Information/Communication Systems   Integrated Circuits   Intelligent Vehicles   Network technology, Security   Networking   Networks and telecommunications research   NEURAL NETWORKS   Reconfigurable Computing   Signal processing   Systems Engineering   Vehicle technology   Very Large Scale Integration (VLSI)   Wireless Networks
Project Title
 Harmonic-AI
From
01/04/2025
To
31/03/2027
Summary
Harmonic-AI is a project led by Dr. Shreejith Shanker , with co-lead Prof. Biswajit Basu, aiming to address stability concerns arising from the widespread adoption of solar photovoltaic systems and electric vehicle (EV) charging. The research focuses on developing low-power, efficient AI models to predict the impact of renewable generation and dynamic EV charging, leading to the creation of an automated smart controller for optimised energy flow without costly infrastructure upgrades.
Funding Agency
Sustaintable Energy Authority of Ireland
Programme
SEAI RDD 2024
Project Type
RDD
Person Months
144
Project Title
 Light-weight Distributed Intrusion Detection for Automotive Networks
From
01/04/2021
To
Summary
Modern vehicles are complex machines driven by electronics, sensors and software. Increasingly, they have become targets for malicious code injections and attacks. Connectivity within a vehicle, predominantly based on legacy networks like CAN, has not evolved to cater to such attacks, while complex rule-based attack detection and prevention systems are inefficient (cost, energy etc). Deep Learning (DL) based solution offers a promising route - however, the computational complexity of DL networks needs to be addressed. This project explores a system-level architecture that enables DL-based intrusion detection to be integrated seamlessly into existing automotive networks. The key challenges we are trying to solve is the low-latency requirements for line-rate detection and the energy overheads of DL-based methods.
Funding Agency
TCD Internal
Project Title
 AI and Process Automation for Sustainable Entertainment and Media
From
To
Summary
EMERALD is a 30-month IA to develop and demonstrate exemplary tools for the digital entertainment and media industries using AI Machine Learning and Big Data technologies, to automate and speed processing, increase production efficiency, use less energy and increase the quality of content. There is a massive increase in the volume of video-based and extended reality content, with an unsustainable demand for skilled human resources, data processing and energy. EMERALD aims to meet the challenge by developing process automation for sustainable media creation; creating a testbed for measuring the energy used in media computation; developing more efficient data use for AI/ML in entertainment and media applications; reducing the power demands for large-scale media data processing; and creating acceptance and demand for AI and sustainable production technologies in the entertainment and media industries. The interdisciplinary Consortium of seven partners includes leading companies from the movie, broadcast, streaming and live entertainment technology sectors, supported by two major European universities.
Funding Agency
HORIZON-IA
Programme
HORIZON-CL4-2022-DIGITAL-EMERGING-02
Project Type
Innovation Action
Project Title
 Brain Health Evaluation using Machine Learning on Ear-EEG Data
From
01/09/2024
To
Summary
Neurological disorders are the second highest cause of death globally, including Alzheimer"s Disease (AD), the most common neurodegenerative disease and most prevalent form of dementia. In Ireland, approximately 64,000 people live with dementia, projected to rise to 150,000 by 2050. While neurodegenerative diseases are incurable, research suggests that modifying key lifestyle factors including smoking and alcohol intake could delay or prevent 40% of dementias. The brain-age gap, the difference between predicted and chronological brain age, has been proposed as a tool for assessing brain health. Mild Cognitive Impairment (MCI), a preclinical stage of AD, results in an increased brain-age gap of +6.2 years, suggesting that the brain-age gap can give an early indication of AD. However, this approach relies on MRI imaging which is expensive and infeasible for continuous monitoring. Traditional scalp electroencephalography (scalp-EEG) has been shown to identify AD with an accuracy of 90% using a Support Vector Machine (SVM) model. However, scalp-EEG would still be unsuitable for regular monitoring of brain health as it requires a specialist to perform. The proposed research explores Ear-EEG as a potential alternative to scalp-EEG, with studies showing it can predict a significant portion of scalp-EEG data. As it is possible to reconstruct scalp-EEG data from ear-EEG using various ML models and scalp-EEG readings can be used to identify brain degeneration such as AD, it follows that ear-EEG could be an alternative tool for assessing brain health.
Funding Agency
Trinity Doctorate Research Award
Programme
Trinity Doctorate Research Award
Project Title
 Resource-efficient Deep-Learning for Microwave Breast Image Reconstruction
From
To
Summary
In this project, the use of machine learning for microwave breast image reconstruction is to be explored. Specifically, this project will examine two key questions: firstly, the feasibility of directly learning a microwave breast imaging reconstruction algorithm that is generalisable and stable; secondly, the development of a custom digital design for a resource-efficient implementation of a fully learned reconstruction algorithm. Together, these questions help assess if recent developments in medical imaging could help accelerate the translation of highly efficient microwave breast imaging to clinical use
Funding Agency
TCD
Programme
Ussher Fellowship

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Details Date
Reviewer and TPC member for International Conferences on FPT, FPL, DATE, HEART, ISCAS
Expert reviewer for IEEE (TVT, TCAS, OJCAS, TBioCAS, TCE, TDSC, ESL, Networking Letters, TCPS, TIFS), Springer CSSP journals, ACM TRETS and ACM TECS
Invited Reviewer for UKRI Research Proposals
External Examiner with the School of Electronic Engineering, DCU (2026-2030) 2026
Language Skill Reading Skill Writing Skill Speaking
English Fluent Fluent Fluent
Malayalam Fluent Fluent Fluent
Details Date From Date To
Member, Association for Computing Machinery 2023
Fahmy, Suhaib A and Vipin, Kizheppatt and Shreejith, Shanker, Virtualized FPGA accelerators for efficient cloud computing, 2015 IEEE 7th International Conference on Cloud Computing Technology and Science (CloudCom), International Conference on Cloud Computing Technology and Science (CloudCom), 2015, pp430--435 , Conference Paper, PUBLISHED
Shreejith, Shanker and Fahmy, Suhaib A., Security Aware Network Controllers for Next Generation Automotive Embedded Systems, Proceedings of the 52nd Design Automation Conference (DAC), 2015, Conference Paper, PUBLISHED
Li, Changhong and Basu, Biswajit and Shanker, Shreejith, LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-learning Accelerators, International Conference on Field Programmable Technology (ICFPT), 2025, Notes: [International Conference on Field Programmable Technology (ICFPT)], Conference Paper, PUBLISHED
Khandelwal, Shashwat and Shreejith, Shanker, SecCAN: An Extended CAN Controller with Embedded Intrusion Detection, IEEE Embedded Systems Letters, 2025, Journal Article, PUBLISHED
Eashan Wadhwa, Georgios Floros, Shanker Shreejith, Context-aware Simopt-Power: Using structural data with simulation metadata to optimise FPGA designs, International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), Germany, Aug, 2026, edited by IEEE , 2026, Conference Paper, PUBLISHED
S. Khandelwal, J. Petri-Koenig, T. B. Preußer, M. Blott and S. Shreejith, FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs, International Conference on Field Programmable Logic and Applications (FPL), 2025, Conference Paper, PUBLISHED
Wadhwa, Eashan and Shreejith, Shanker, Simopt-Power: Leveraging Simulation Metadata for Low-Power Design Synthesis, 2025 IEEE Nordic Circuits and Systems Conference (NorCAS), IEEE Nordic Circuits and Systems Conference (NorCAS), 2025, pp1--6 , Conference Paper, PUBLISHED
Guoxin Wang, Shreejith Shanker, Avishek Nag, Yong Lian, Deepu John, ECG Biometric Authentication Using Self-Supervised Learning for IoT Edge Sensors, IEEE Journal of Biomedical and Health Informatics, 2024, Journal Article, PUBLISHED
Shashwat Khandelwal, Shanker Shreejith, A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN, International Conference on Field Programmable Technology, Hong Kong SAR, China, IEEE, 2022, Conference Paper, PUBLISHED  TARA - Full Text
Anneliese Walsh, Shreejith Shanker, Alejandro Lopez Valdes, Multiclass Differentiation of Dementia Subtypes Based on Low-Density EEG Biomarkers: Towards Wearable Brain Health Monitoring, Journal of Dementia and Alzheimer's Disease, 2, (4), 2025, p48 , Journal Article, PUBLISHED  DOI
  

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Award Date
Best Paper Award - IEEE COINS, 2022 for our paper titled "FPGA-based Deep-Learning Accelerators for Energy Efficient Motor Imagery EEG classification" 2022
My research centres on novel computer architectures that enhance compute efficiency, optimise resource and energy consumption, and provide real-time adaptivity through the seamless co-design of software and hardware. Since joining Trinity College Dublin in 2019, my research programme has established four primary pillars: * Neural Network Optimisations: Developing algorithms to compress and optimise compute-intensive deep neural networks, significantly reducing energy consumption, silicon footprint (area), and execution latency, enabling AI-driven solutions in energy and resource constrained applications. * Communication-Layer Architecture: Embedding security, virtualisation, and performance enhancements into communication layers for safety-critical and high-performance systems, allowing seamless integration of novel compute functions in a manner that is transparent to the end-users / applications. * Custom Tooling Infrastructure: Building open-source and internal software tools for performance profiling, granular energy monitoring, neural network compression, and compiler/mapping flows, which enable bespoke optimisations and energy-performance-resource tradeoffs. * Metadata-Driven EDA Optimisation: Integrating early-stage logic simulation metadata into CAD and Electronic Design Automation (EDA) flows to enable energy-aware physical synthesis, placement, and routing, improving the efficiency of the end design. This work spans the full computing spectrum"from embedded and edge devices to high-performance cinema post-production media pipelines"across CPUs, GPUs, FPGAs, and ASICs. Looking ahead, my agenda focuses on advancing theories, tools, and practices in adaptive computing to tackle real-world challenges in AI acceleration, compute-in-network systems, and sustainable hardware design. Since 2021, my research group has expanded from a single doctoral candidate into a multi-disciplinary team comprising four primary PhD students, two co-supervised PhD students, two Research Assistants, and one Postdoctoral Fellow. The group is poised for further growth in autumn 2026 with an incoming PhD student, two Research Assistants, and an additional co-supervised PhD candidate. * Supervision & Mentorship: Graduated my first PhD student in 2025, with a second thesis submission targeted for early 2027. My first Postdoctoral Fellow completed their project in early 2026 and has since transitioned into an industrial research role. * Research funding: Secured competitive funding across national, European, and commercialisation streams, including two Sustainable Energy Authority of Ireland (SEAI RDD) awards, European Horizon Research and Innovation Actions (RIA) grants, and Enterprise Ireland (EI) Commercialisation Funds. I have established an international standing within reconfigurable computing (FPGAs) and embedded computer architecture. Peer recognition of my work is reflected in invitations to join international research consortia, serve on Technical Program Committees (TPCs), organise academic conferences, review for leading IEEE and ACM journals, and deliver expert talks. My ongoing objective is to extend this standing leadership through EU and international project consortium roles and by bidding to bring flagship international conferences in reconfigurable computing and circuit design to Dublin.