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Dr. Shreejith Shanker

Assistant Professor (Electronic & Elect. Engineering)
ARAS AN PHIARSAIGH


Dr. Shreejith is an Assistant Professor at the Department of Electronic & Electrical Engineering at Trinity College Dublin, The University of Dublin, Ireland, since April 2019. He graduated with a Bachelors degree in Electronics & Communication Engineering from the former the University of Kerala {currently called APJ Abdul Kalam Technological University} in 2006 and a PhD degree from Nanyang Technological University and Technical University of Munich in 2016. From 2015 to 2016, he was a post-doctoral research fellow at the Hardware and Embedded Systems Lab, Nanyang Technological University, Singapore where he was working on cognitive radio architectures and techniques for commercial and aeronautical communication systems. He took up the role of Teaching Fellow at the School of Engineering, The University of Warwick, UK in 2017, where he continued his research on in-network computation and accelerators, while primarily focussing on delivering modules on Computer Architecture and Programming to the undergraduate cohort. He briefly took up the role of Research Fellow at the Electrification Suite and Test Lab , TUM CREATE Ltd, Singapore, exploring research ideas on decentralised compute systems in smart energy systems and power grids before taking up the role of Assistant Professor at Trinity College Dublin, Ireland. His current research explores reconfigurable architectures and frameworks for distributed accelerators that are tightly coupled to the network fabric, with application to autonomous systems, media processing and communication networks. He started his professional career in 2006 as a Design Engineer at Processor Systems India where he was involved in design and verification of high-speed custom logic for network switches and compute accelerators. Later, he joined the Vikram Sarabhai Space Centre, one of the premier research centres under the Indian Space Research Organisation as a Scientist working on design of real-time, mission critical subsystems for launch vehicles and satellite systems.
  Applied Electronics   ARTIFICIAL NEURAL NETWORKS   Automotive Electronics   Communication engineering, technology   Communication Systems   Communications engineering   Computer architecture   Computer Hardware   Computer Networks   Computer/Data/Network Security   Data protection, storage technology, cryptography   Digital Computers/Computing   Digital systems, representation   Distributed systems   Electrical Engineering/Electronics   Electronic circuit design   Electronic Engineering, circuit design   ELECTRONICS   Embedded computing   Field Programmable Gate Arrays (FPGAs)   High Performance Computing   Information/Communication Systems   Integrated Circuits   Intelligent Vehicles   Network technology, Security   Networking   Networks and telecommunications research   NEURAL NETWORKS   Reconfigurable Computing   Signal processing   Systems Engineering   Vehicle technology   Very Large Scale Integration (VLSI)   Wireless Networks
Shivaraman, Nitin and Ramanathan, Saravanan and Shanker, Shreejith and Easwaran, Arvind and Steinhorst, Sebastian, DeCoRIC: Decentralized Connected Resilient IoT Clustering, International Conference on Computer Communications and Networks (ICCCN), USA, 2020, Conference Paper, PUBLISHED  TARA - Full Text
Emanuel Regnath, Nitin Shivaraman, Shanker Shreejith, Arvind Easwaran, Sebastian Steinhorst, Blockchain, what time is it? Trustless Datetime Synchronization for IoT, International Conference on Omni-layer Intelligent Systems (COINS), Barcelona, Spain, September, 2020, 2020, Conference Paper, PUBLISHED  TARA - Full Text
Mathew, Libin K and Shanker, Shreejith and Vinod, AP and Madhukumar, AS, A Power-Efficient Spectrum-Sensing Scheme Using 1-Bit Quantizer and Modified Filter Banks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28, (9), 2020, p2074--2078 , Journal Article, PUBLISHED
Bucknall, Alex R and Shreejith, Shanker and Fahmy, Suhaib A, Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration, International Conference on Field Programmable Technology (ICFPT), 2019, Conference Paper, PUBLISHED
Mathew, Libin K and Shanker, Shreejith and Vinod, AP and Madhukumar, AS, An Adaptive Energy Detection Scheme with Real-Time Noise Variance Estimation, Circuits, Systems, and Signal Processing, 2019, p1--25 , Journal Article, PUBLISHED
Shreejith, Shanker and Cooke, Ryan A and Fahmy, Suhaib A, A smart network interface approach for distributed applications on Xilinx Zynq SoCs, 2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018, pp186--1864 , Conference Paper, PUBLISHED
Shreejith, Shanker and Mathew, Libin K and Prasad, Vinod A and Fahmy, Suhaib A, Efficient spectrum sensing for aeronautical LDACS using low-power correlators, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26, (6), 2018, p1183--1191 , Journal Article, PUBLISHED
Shreejith, Shanker and Fahmy, Suhaib A, Smart network interfaces for advanced automotive applications, IEEE Micro, 38, (2), 2018, p72--80 , Journal Article, PUBLISHED
Ambede, A. and Shreejith, S. and Vinod, A.P, Efficient FPGA Implementation of a Variable Digital Filter based Spectrum Sensing Scheme for Cognitive IoT Systems, Global IoT Summit, 2017, Conference Paper, PUBLISHED
Warrier, Rakesh and Shreejith, Shanker and Zhang, Wei and Vun, Chan Hua and Fahmy, Suhaib A, Fracturable DSP block for multi-context reconfigurable architectures, Circuits, Systems, and Signal Processing, 36, (7), 2017, p3020--3033 , Journal Article, PUBLISHED
  

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My research area focuses on building computer architectures that enable unique ways for improving compute efficiency, network performance and provide reactive capabilities to adapt to changing environments, through seamless interaction of software and hardware. I have applied this approach to tailor compute/network architectures in different domains such as automotive embedded systems, cognitive radio systems and internet of things. A key enabler for his research is fully programmable platforms (or reconfigurable hardware), which enables both the software and the underlying hardware to be adapted to the compute requirements and specifications, either statically (i.e., at design time) or dynamically (i.e., at run-time). My current research focusses on decentralised compute architectures, in-network computation and domain specific accelerators with the aim of pushing compute closer to the producers and consumers of information in connected systems.